D_pipeline Project Status
Project File: CPU.xise Parser Errors: No Errors
Module Name: D_pipeline Implementation State: New
Target Device: xc6slx100-2fgg676
  • Errors:
  
Product Version:ISE 14.7
  • Warnings:
  
Design Goal: Balanced
  • Routing Results:
  
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
  
Environment:  
  • Final Timing Score:
   
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis Report     
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogCurrentÖÜÁù 11ÔÂ 9 14:46:44 2024

Date Generated: 11/09/2024 - 15:21:41